The disclosure relates to a method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same.
Due to high degree of integration of semiconductor devices, the size and pitch of patterns included in a semiconductor device have decreased.
A spacer patterning technology (SPT) using three exposure masks has been suggested in order to obtain a highly-integrated, fine pattern even with conventional equipment.
In order to overcome the resolution limit of optical lithography, the SPT method includes a mask process and an etching process which are repeated several times. The manufacturing of devices using the SPT method includes forming a layout through a design flow which has been previously used by a designer, and decomposing the layout into a plurality of mask layouts by hand.
The mask layouts are applied to an actual process to identify problems. The problems are then corrected to form a final mask layout.
It is difficult to identify whether a pattern intended by a designer is formed over a wafer in the above-described conventional art. In other words, it is difficult to determine where problems occur before confirmation of a result of a pattern formed over a wafer.
Since patterns are divided manually in a pattern decomposing process, it takes a large amount of time, and it is possible to generate errors in the pattern decomposing process. Also, due to many process steps, it is difficult to obtain feedback in a short time.